The present invention relates to a semiconductor memory device; more particularly, to a data input circuit for use in the semiconductor memory device and a method for controlling an operation thereof.
The semiconductor memory device stores data and outputs the data stored. The semiconductor memory device comprises a data storage area and an I/O peripheral area. In the data storage area, there are a plurality of unit cells for storing data, and in the I/O peripheral area, there is a data I/O circuit for outputting data stored in the data storage area or transmitting external data into the data storage area.
The I/O area includes a data input circuit, a data output circuit, an address input circuit and a command input circuit. The data input circuit delivers external data into the data storage area in response to a write command. The data output circuit outputs data, stored in the data storage area, to an external device in response to a read command. The address input circuit decodes an input address representing the location of the data corresponding to input and output operations. The command input circuit receives the read and write commands and controls other circuits.
Semiconductor memory devices are required to input/output data at increasingly higher speed. As technology has advanced, an operating speed of a system including a semiconductor memory device has increased. At first, a synchronous semiconductor memory device was designed for transmitting data at high speed. The synchronous semiconductor memory device would input data synchronized with a clock signal. However, as an operating speed of a system including the semiconductor memory device has continued to increase, a DDR synchronous semiconductor memory device, which inputs or outputs data on both of the rising and falling edges of a clock signal, has been designed.
There are challenges for semiconductor memory device that inputs data on both of the rising and falling edges of a clock signal. Because a delay time is introduced when the clock signal and the data are transmitted to the semiconductor memory device, the semiconductor memory device may not receive the data accurately synchronized with transitions of the clock signal if the system operates at a very high speed.
Due to delay times introduced when the clock signal and the data are transmitted, the existing margin for transmitting one piece data into the semiconductor memory device on every half period of the clock signal is insufficient. Accordingly, a DDR synchronous semiconductor memory device does not input data corresponding to the transition of the clock signal but a data strobe signal. Herein, the data strobe signal is transited with the input timing of the data. A semiconductor device transmitting the data generates the data strobe signal when it outputs data, and inputs the data strobe signal into the semiconductor memory device. The semiconductor memory device inputs the data corresponding to transitions of the data strobe signal. However, the semiconductor memory device uses the clock signal for internal operations based on read and write commands.
Meanwhile, the semiconductor memory device performs a prefetch operation to input a plurality of pieces of data at high speed. The prefetch operation is for aligning a plurality of data input in succession to convert it to parallel data. Because the parallel data are processed simultaneously in the data storage area, a plurality of data pieces can be processed at high speed. In order to increase operating speed, the semiconductor memory device requires a circuit which receives a plurality of data input in succession and aligns the data. If the size of the pieces of data which are input to one data input circuit in one write operation is 4 bits, it means performing 4 bit prefetch operations.
The data input circuit inputs data in response to the transition of the data strobe signal. Pieces of data input in succession are aligned and converted into parallel data. The data input circuit transmits the parallel data to the data storage area, according to a signal synchronized with the clock signal.
FIG. 1 illustrates a block diagram of a conventional semiconductor memory device. In particular, the data input circuit of the semiconductor memory device is described. The data input circuit includes a data aligning unit 10, an aligning signal generator 20, a clock buffer 30, multiplexer 40, a data transmitter 50 and an writing driver 60.
The data aligning unit 10 includes a data input buffer 11 and a plurality of latches 12 to 18. The data input buffer 11 receives and buffers external data DIN, and outputs to latches 12 and 14. The plurality of latches 12 to 18 latches data, input from the input buffer 11 in order of precedence, in response to the aligning signals DSRP4 and DSFP4. The plurality of latches 12 to 18 aligns and outputs 4 pieces of data AL_R0, AL_F0, AL_R1 and AL_F1 in parallel to the multiplexer 40.
The aligning signal generator 20 generates and outputs the aligning signals DSRP4 and DSFP4, respectively synchronized with rising and falling edges of the data strobe signal DQS. The clock buffer 30 generates a data transmitting signal DP, synchronized with the transition of an internal clock signal ICLK, in response to a clock enabling signal EN_ICLK.
The multiplexer 40 outputs a data signal AL_D to the data transmitter 50. The multiplexer is used when the semiconductor memory device operates in every mode, such as X4, X8 and X16 modes. Because all of the data input circuits receive data in the X16 mode, the multiplexer does not need to operate. However, only 4 or 8 number of data input circuits operate in the X4 or X8 modes respectively. Because each data transmitting line corresponds to each data input circuit, the data can be transmitted to the corresponding data transmitting line by the multiplexer 40.
The data transmitter 50 receives and amplifies the data signal AL_D, output from the multiplexer 40, in response to the data transmitting signal DP. The data transmitter 50 outputs a data signal GIO to the writing driver 60. The writing driver 60 transmits a data signal pair GIO and GIOB to the data storage area.
The parallel data AL_R0, AL_F0, AL_R1 and AL_F1, output from the data aligning unit 10, are synchronized with the data strobe signal. However, the data transmitter 50 transmits the data signal, synchronized with the data transmitting signal DP. Thus, a basis signal for the data transmission is changed from the data strobe signal into the clock signal. Herein, the change of the basis signal for the data transmission is referred to as a domain crossing.
FIG. 2 illustrates a signal timing diagram of the semiconductor memory device described in FIG. 1. The data strobe signal DQS is transitioned corresponding to a data input timing and input to the semiconductor memory device. The operating margin of the data strobe signal DQS is a half cycle of the clock. This means that the difference between the input timings of the earliest and latest strobe signals DQS is a half cycle of the clock. Because the operating margin of the data strobe signal DQS is half of the clock, the operating margin for the data aligning unit 10 to align the data is a quarter cycle of the clock.
Thereafter, the aligning signals DSRP4 and DSFP4 are generated, respectively corresponding to rising and falling transitions of the data strobe signal DQS. Pieces of data are aligned in response to the aligning signals DSRP4 and DSFP4. At points A1 and A2 described in FIG. 2, 4 pieces of data are aligned. The data transmitting signal DP is generated by performing a logic operation based on the clock enabling signal EN_ICLK and the internal clock signal ICLK, which is buffered from the clock signal. The aligned data are transmitted to the next stage in response to the data transmitting signal DP.
As technology develops, a clock signal of a system including the semiconductor memory device has increasingly higher frequency. An input speed of data to the semiconductor memory device is consequently increased. Accordingly, an operating margin of the data input circuit is decreased. An operating margin for a domain crossing, i.e., a time margin for aligning the data based on the aligning signals and transmitting the data in response to the data transmitting signal DP, is also decreased.
According to conditions of a manufacturing process or the level of temperatures and supply voltages during operation, operation performance characteristics of the semiconductor memory device will change. At a high clock signal frequency, even if the operation performance only changes a little, the data input circuit of the semiconductor memory device may nevertheless operate in excess of its operating margin. It is possible that the data input circuit will operate abnormally because the data input circuit can not perform required operations within the necessary amount of time. In particular, within the necessary amount of time, the margin that the clock buffer generates and transmits the data transmitting signal may be absolutely insufficient.
In addition, a ring back of a clock signal can be caused at high frequencies, which results in malfunctioning of the data input circuit. This is illustrated at point A3 in FIG. 2. The ring back represents that the transition of the data strobe signal is dominated by noise. If the transition of the data strobe signal occurs without any data input, defective data can be transmitted to the data storage area through the data input circuit. As the input margin of the data transmitting signal, which is input to the data transmitter, is decreased, ring back has more influence on operation. Thus, normal data may be substituted with faulty data.